68020

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68020

Postby Chris » Tue Feb 11, 2014 8:57 pm

I just received a book on the 68020/030 procesors that I purchased on ebay for 99p.

Marvel of marvels it has a circuit for a 68020 synchronous interface on page 11 :o , well worth the 99p already

I will have to build it and see how well it performs.
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Re: 68020

Postby simon » Tue Feb 11, 2014 10:15 pm

Cool, a synchronous interface. :) How fast is the E clock? Still 1MHz to be compatible? Then this interface would be the solution to connect the SIDs... :)
Could you scan page 11? :roll:
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Re: 68020

Postby Chris » Wed Feb 12, 2014 10:57 am

simon wrote:Cool, a synchronous interface. :) How fast is the E clock? Still 1MHz to be compatible? Then this interface would be the solution to connect the SIDs... :)

It uses a counter so it could be modified to accept any master clock that could be divided down to 1Mhz, so even 32Mhz processor clock would be achievable it would just mean more wait states when talking to the SIDs.

I also found another hidden away in a another book but it is much more complicated and seems to use 2 E clocks for each transaction. I'm not sure how a SID would cope with that maybe do a double write which may or may not manifest itself as a glitch in the audio, again it would need some experimentation.

simon wrote:Could you scan page 11? :roll:


Certainly, I'll try and do it tonight.

Regards

Chris
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Re: 68020

Postby Chris » Wed Feb 12, 2014 7:12 pm

Async.jpg
Async.jpg (98.7 KiB) Viewed 17171 times


It could be quite easy to implement as a state machine.
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Re: 68020

Postby simon » Wed Feb 12, 2014 11:13 pm

Cool! Thank you, Chris! This could be very useful in the future. :)
Though I must admit that I have to understand the circuit first. Maybe I should keep my eyes open for a good 68020 book. :)
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Re: 68020

Postby mk279 » Wed Apr 30, 2014 7:16 pm

Hi,

I paste a state machine for the /DTACK generation for the SID (using only discrete logic ;) )
Since the synchronous interface is not used, the clocking of the CPU is more independent of the SID clock.
Then the 68020 could be easily connected to the SID.
I use the 1/8 clock divisision with a CPU clock of 8MHz (68000 and 68010), but you could easily extend the divider to support other clock speeds.

Maybe it's of use for you in an FPGA?

Regards,
Martin

sid.png
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Re: 68020

Postby HiroProX » Sat Jul 05, 2014 7:13 pm

Admittedly a 020 introduces new complexities. Part of why in my own 68K design I plan to use the only 68K cpu more odd than the 68008, the 68012. Its essentially a 68010 with two 30-bit flat address ranges.
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